SC Filter Designer Tutorial: Step-by-Step Circuit Examples

SC Filter Designer Best Practices: Layout, Component Selection, and Testing

Placement: Put switches and capacitors for each switched-capacitor (SC) stage close together to minimize parasitic routing between series nodes.
Routing: Route critical clock and switch signals with short, matched-length traces; use a separate, low-impedance return for clock drivers.
Shielding: Place grounded shields/guard rings between high-impedance nodes and noisy digital/clock lines.
Floorplanning: Group analog blocks (input, SC stages, output buffer) away from digital logic; route clocks along the shortest path with minimal bends.
Symmetry: Mirror differential layouts to balance parasitics and reduce even-order distortion and offset.
Common-centroid: Use common-centroid capacitor layouts for matched capacitor arrays to cancel gradient/processing variation.
Decoupling: Place local decoupling caps close to supply pins of switches/drivers; use multiple values (e.g., 10 nF + 100 pF) for broad-frequency rejection.

Capacitors: Use high-linearity, low-ESR MIM or high-quality metal-oxide capacitors when available; size capacitors to trade thermal/quantization noise vs. area (larger C → lower kT/C noise, slower settling).
Switches/Transistors: Choose transistors with adequate on-resistance (Ron) vs. clock feedthrough; larger devices reduce Ron but increase charge injection—balance with device sizing and dummy switches.
Clock drivers: Use low-jitter, low-skew clock drivers; ensure drive strength matches capacitive load without excessive ringing.
Buffers/OTAs: Select amplifiers with bandwidth and slew-rate sufficient for required settling in each phase; ensure noise and distortion specs meet SNR targets.
ESD and protection: Avoid large protection diodes directly on critical nodes; use series resistors or carefully designed clamps to limit added parasitics.
Passive tolerances: Account for capacitor mismatch and temperature coefficients in sizing and calibration strategy.

Test points: Provide accessible analog test points for key nodes (inputs, mid-stage nodes, outputs) and clock observation points.
Clock verification: Measure clock duty cycle, rise/fall times, jitter, and phase relationships on silicon under load; verify matching between complementary phases.
Settling tests: Apply step inputs and verify settling time and error for each phase; confirm OTA settles within allotted phase time across PVT corners.
Noise and SNR: Measure input-referred noise and SNR using appropriate windowing; verify kT/C noise scales with capacitor size as expected.
Distortion: Run THD/SINAD tests with sine inputs across frequency and amplitude ranges; check for charge-injection-induced spurs and mismatch distortion.
Mismatch characterization: Perform capacitor and switch mismatch measurements (e.g., apply code-dependent tests) to quantify and calibrate offset/gain errors.
Corner/temperature testing: Exercise across supply, process corners, and temperature extremes to confirm stability and timing margins.
Automated wafer tests: Implement production test vectors: clock integrity, functional switching, basic linearity, and a short settling/noise/offset screen that fits tester time budget.
Debug aids: Include extra scan or reconfigurable clock paths to isolate stages during debug; consider on-chip calibration DACs or trimming elements to correct mismatch.

Layout: short routes, shields, symmetry, common-centroid for caps.
Components: choose low-noise caps, balanced transistor sizing, adequate OTA BW/settling.
Testing: verify clocks, settling, noise, distortion, and perform PVT sweeps plus production-friendly tests.

If you want, I can produce a one-page PCB/IC layout checklist or a sample test plan with specific measurements and pass/fail limits.